LogicWorks(TM) Lab 4

Logic Simulation of Circuits with Feedback

1. Tutorial Objectives

In this laboratory, you will gain experience in using LogicWorks(TM) to simulate latches, flip-flops, and some simple shift register circuits. In particular, you will:

* Simulate ring oscillators constructed from inverter chains.

* Simulate R-S and - latches constructed from cross coupled NOR gates and NAND gates respectively.

* Simulate a master/slave J-K flip-flop.

* Simulate positive and negative edge-triggered D flip-flops.

* Construct a two element shift register and determine the conditions under which the introduction of clock skew leads to incorrect results.

* Understand the limitations of the software simulator for simulating circuits with feedback, particularly for modeling race conditions, and how to establish initial conditions for the simulator.

Look back at Lab One if you need to review the use of LogicWorks(TM). It will be useful to remember how to use the Device Editor introduced there.

2. Getting Started: Ring Oscillators

1. Begin by invoking LogicWorks(TM), and create a schematic with three inverters in series.

2. Feed the output of the last inverter stage back as an input to the first stage.

3. Place probes at the outputs of the three inverter.

4. Label the outputs of each inverter by the labels A, B, and C respectively..

What value do they read out?

The simulator must commence its operation making some assumptions about the initial values of all circuit nodes.

LogicWorks(TM) understand the values

· logic 0,

· logic 1,

· undefined ( "X" ),

· as well ( "Z" ).

Initialize the simulation
In the absence of other information, LogicWork assumes that all circuit nodes are undefined. One way to initialize the simulation to a known state is to use the Select All under Edit then Clear Unknowns command under the Simulation menu. Do this now.

1. What happens to the values displayed on the probes?

2. Is this an inconsistent starting state for the simulation?

3. If so, why?

While clearing the unknowns using the simulator command certainly has its uses, it is better to explicitly place the simulation in a known state. By the way, this is also a good idea in real hardware: at power up, a hardware system can (and as Mr. Murphy would said, will) come up in an unexpected or inconsistent state.

Place the simulation in single step mode. The simplest way to initialize the simulation is to specify starting waveforms in the timing window that are consistent. Do this then place initial values on A, its complement on B, and B's complement on C by selecting a line and right clicking. Choose attributes then Initial Sig and place value in box and check visible.

4. What waveforms are displayed in the timing window?

Run, Watch the values as they pass through the probes. If you see an "X" value that persists, you have not succeeded in correctly initializing the simulation. Single step the simulation if you are having difficulties following how the values change. It is not inconsistent in a running simulation for the input and output of an inverter to have the same value.

5. Why is this?

Set duty cycle

6. What is the period of the output waveforms, i.e., how many time units are there between adjacent rising edges?

7. What is the duty cycle of the waveforms, i.e., the percentage of time that the waveform is high versus low during its period?

8. How wide, in time units, is the high time of the waveform?

It may be difficult to answer these questions because LogicWorks(TM) assumes unit delay, that is, each gate has a delay of one time unit. Go back and increase the gate delays to ten time units for each inverter. (Reminder: to do this, first select the gate, then select the Set Params command under the Simulation menu, and finally fill in 10 in the delay box.)

9. Now what is the period, duty cycle, and high time of the waveforms?

Extend the circuit to five inverters in a chain.
If you changed the delay of the inverters in the preceding paragraph, don't forget to follow the same process for the inverters you are now adding to the chain. You will probably need to reset the timing and re-initialize the simulation to get it into a consistent starting state.

10. What do the waveforms look like now?

11. What is the relationship between the number of gates in the chain and the shape of the waveform?

Clock
Under the Generic Devices submenu of the Libraries menu, you will discover a useful device called clock. Select this and place it on your schematic. Put a probe on its output and label it CLK. Select the device and then Select Params under the Simulation menu. LogicWorks(TM) allows you to set the high and low times of your clock. By default it has a period of 20 time units with a 50% duty cycle (i.e., high time of 10 time units, low time of 10 time units). Experiment with different settings and verify through simulation that the clock generates the waveform you specified.

3. R-S and Latches

With LogicWorks(TM), draw two cross-coupled NAND gates and two cross coupled NOR gates. Places switches at the inputs and probes at the outputs. Call the outputs Qnand, , Qnor, and , and the inputs In1, In2, In3, and In4 (as shown in Figure 1)

.

Figure 1

What are the initial values read out on the probes? Do they include don't cares? If they do, place the latches in a consistent initial state. Now try all input combinations and write down your observations in a table format.

In terms of setting and resetting the outputs,
what function is formed by driving

1. In1 low (to 0)?

2. In2 low?

3. In3 high (to 1)?

4. In4 high?

5. Under what conditions are the outputs, supposedly complementary, driven to the same values?

6. Circle these "forbidden" states in your table.

7. Under what conditions do the latches hold their previous values?

8. Typical setting means forcing a value to 1 and reset means forcing it to 0. Rename your inputs S for the input which performs set and R for reset.

9. Describe what is meant by race conditions. (It is not possible to observe the race condition inherent in latches implemented as above when using the input switches. Both inputs must change simultaneously to trigger the race.)

“level sensitive” latch
For the rest of this laboratory, we will be using the R-S latch to build other kinds of building blocks. Create the following “level sensitive” latch and built from a copy of the RS latch.

10. How does this behave compared to the RS latch?

11. Can it change state back and forth while the CLK input is at logic 1

12. Are set and reset active high or active low?

Make level-sensitive D-latch from level-sensitive RS-latch by connecting S = D and R = not D.

1. How does this latch behave? (give a table)

2. Describe why this configuration avoids the "forbidden state" problem.

4.Master/Slave Edge-triggered Flip-flop

First, construct a flip-flop using the D latch as a building block.

1. What is the behavior of this flip-flop?

2. Does this value of Q at time t+1 depend on Q at time t?

3. What does it depend on?

4. Explain how the master slave configuration and making the flip-flop edge-triggered, makes certain that we can precisely control the moment when all flip-flops will change state.

5. If this were built with R-S latches instead of D latches (an RS flip-flop) how would feedback from slave to master help avoid the "forbidden state" problem?

5.Toggle Flip-flops

Build the following flip-flop where D-latch is a copy of your level sensitive latch above.

1. What is the behavior of this flip-flop?

2. determine what happens when J and K are both 1

Factoid: Ripple Counter

In the 4-bit counter to the right, we are using edge-triggered master-slave flip-flops similar to those above. The output of each flip-flop changes state on the falling edge (1-to-0 transistion) of the T input.

The count held by this counter is read in the reverse order from the order in which the flip-flops are triggered. Thus, output D is the high order of the count, while output A is the low order. The binary count held by the counter is then DCBA, and runs from 0000 (decimal 0) to 1111 (decimal 15). The next clock pulse will cause the counter to try to increment to 10000 (decimal 16). However, that 1 bit is not held by any flip-flop and is therefore lost. As a result, the counter actually reverts to 0000, and the count begins again.

A major problem with the counters shown on this page is that the individual flip-flops do not all change state at the same time. Rather, each flip-flop is used to trigger the next one in the series. Thus, in switching from all 1s (count = 15) to all 0s (count wraps back to 0), we don't see a smooth transition. Instead, output A falls first, changing the apparent count to 14. This triggers output B to fall, changing the apparent count to 12. This in turn triggers output C, which leaves a count of 8 while triggering output D to fall. This last action finally leaves us with the correct output count of zero. We say that the change of state "ripples" through the counter from one flip-flop to the next. Therefore, this circuit is known as a "ripple counter."